Embodiments of the invention relate generally to structures and methods for packaging semiconductor devices and, more particularly, to an electronics package structure that facilitates the integration of different types of electrical components, such as power semiconductor devices and control or digital logic semiconductor devices, in a common package structure.
As semiconductor device packages have become increasingly smaller and yield better operating performance, packaging technology has correspondingly evolved from leaded packaging, to laminated-based ball grid array (BGA) packaging, to chip scale packaging (CSP), then flip chip packages, and now buried die/embedded chip build-up packaging. Advancements in semiconductor chip packaging technology are driven by ever-increasing needs for achieving better performance, greater miniaturization, and higher reliability.
A challenge to existing manufacturing techniques is the miniaturization of electronics packages that incorporate different types of individually packaged electronics components that have different current carrying and routing density requirements, such as a mixture digital logic semiconductor devices and power semiconductor devices.
Numerous different packaging and interconnection technologies are used in the field of power electronics, including hybrid circuits, multichip modules, package-on-board assemblies, and embedded chip modules. Hybrid circuits typically have a multilayer ceramic substrate, wire bonded chips attached to the substrate, and multiple thin film or thick film passive elements formed within or on the substrate. Multichip modules typically have a multilayer organic substrate, wire bonded chips attached to the substrate, and discrete passive devices attached on top on the substrate. Package-on-board assemblies typically include individually packaged semiconductor devices and discrete passive devices surface mounted on a printed circuit board (PCB). Embedded chip power electronics technologies represent a newer packaging approach to power electronics. In this approach, one or more power semiconductor chips is embedded within or under an organic interconnect structure that has one or more organic dielectric layers and patterned interconnect layer over or over and under the chips. A key feature of embedded chip modules is that metallized vias formed through the organic dielectric directly connect to the chip input/output (I/O) pads, eliminating wire bonds and flip chip solder bumps. The via structure has an order of magnitude lower interconnect resistance and interconnect inductance compared to wire bonds or solder bumps.
Many power electronics packages or circuits are used in high voltage power applications and are designed to carry a large amount of current and/or support a large voltage and/or high-power dissipation. These power electronics packages include power semiconductor devices that require interconnection elements that have the capacity to handle high currents and high voltage levels. Power semiconductor devices that are individually packaged, such as a leadless wire-bonded ceramic or plastic chip carriers, include multiple thick wire bonds to connect the high current pads on the chip to the package leadframe. The carrier leadframe and I/O terminals also include thick, wide conductive elements such as pads or leads. Likewise, the circuit board upon which the power chip carrier is mounted includes wide power traces or preferably power/ground planes to provide the desired current carrying capacity.
Typical power electronics circuits also include low or lower power semiconductor devices to provide logic and control functions, including drive circuitry, feedback circuits, and the like. These logic electronics devices have different design requirements than the power semiconductor chip(s) and power interconnection elements, including lower voltage levels, lower current levels, smaller device pads, and more I/O terminals per device.
In typical power electronics using single-chip, chip carrier packages for both high power and logic devices that are mounted on a circuit board, the packages for high power semiconductor devices include structures designed for high voltage, current and power dissipation and the packages for lower power logic components include structures designed for low voltage, current and power dissipation. These packaging structures are solder attached to a power circuit board which has both wide high current carrying traces/planes for the power interconnections and narrow, low current carrying traces.
The fabrication of an embedded chip power module having both high power semiconductor chips and low power logic semiconductor chips is complicated with the concurrent need for thick and thin insulating layers, different interconnect thicknesses for high power semiconductor chips and logic semiconductor chips, and large and small vias. Various approaches have been proposed to efficiently handle the divergent requirements of power semiconductor chips and logic semiconductor chips within the same embedded chip modules. However, these prior art solutions fail to provide reliable interconnect structures that efficiently provide electrical connections for logic or control semiconductor devices within the power module.
Accordingly, there is a need for an embedded power module that efficiently provides interconnections for different types of electrical components, such as high-power semiconductor devices and lower power semiconductor devices, including logic and control components.